1. Field of Use
This invention relates to memory systems and more particularly to transfers of multiple words of data between memory systems and data processing apparatus over a common bus.
2. Prior Art
It is well known to construct memory systems from a number of memory modules. In certain prior art systems, memory modules are paired together to provide a double word fetch access capability. The term double word fetch access as used herein refers to the capability of being able to access a pair of words at a time from a memory system during a cycle of operation. This type of system is described in the copending patent application "System Providing Multiple Fetch Bus Cycle Operation", invented by John L. Curley, Robert B. Johnson, Richard A. Lemay and Chester M. Nibby, Jr., U.S. Pat. No. 4,236,203, issued Nov. 25, 1980 and assigned to the same assignee as named herein.
In the above prior art system, the memory system connects to an asynchronously operated single word wide bus. In the arrangement, a request for multiple words is made in a single bus cycle and the requested information words are delivered to the bus over a series of response cycles. While this arrangement improves the system throughput capabilities, it becomes desirable to be able to provide a memory system with the capability of transferring over a single bus groups of multiple words accessed simultaneously during a series of cycles without incurring communication delays. This becomes desirable where it is necessary to provide a high speed transfer of data to another memory device such as a cache unit or disk device.
Copending patent application "A Memory Controller with Burst Mode Capability", referenced herein, discloses a burst mode capability which is established as a function of the memory request address. That is, the requesting device provides an even address. In some cases, it may not be convenient to have the requesting device specify a certain type of characteristic. Also, certain error situations could alter address information making the controller 200 incorrectly enter a burst mode of operation.
Accordingly, it is a primary object of the present invention to provide a memory controller which is able to respond to memory requests specifying a multiword transfer.
It is a further object of the present invention to provide a memory controller with the capability of transferring groups of data words over a common bus during consecutive bus cycles of operation starting with any word boundary.